In many electronic systems, it is desirable to reduce the supply voltage in digital logic circuits so as to reduce power consumption and thermal heating. However, such low voltage circuits may need to interface with other circuits operating in a different voltage domain. A voltage level shifter provides an interface between two voltage domains. For example, a first voltage domain may operate in which the logic signals take on either the voltage VSS, sometimes referred to as the substrate voltage or ground, and a first supply voltage, VDDL; and a second voltage domain may operate in which the logic signals take on either the voltage VSS or a second supply voltage, VDDH, where VDDH is greater than VDDL. A voltage level shifter receives as input a logic signal in the first voltage domain, and provides as output a logic signal in the second voltage domain where the output logic signal follows the input logic signal.
A large class of voltage level shifters makes use of a cross coupled latch. FIG. 1A illustrates a conventional cross-coupled voltage level shifter. An input logic signal is provided to the input port 110, and the output port 130 provides an output logic signal. The input logic signal is in a first voltage domain with HIGH voltage VCCL and LOW voltage VSS, and the output logic signal is in a second voltage domain with HIGH voltage VCCH and LOW voltage VSS. The output of the driver 120 is coupled to the gate of the nMOSFET (Metal-Oxide-Semiconductor-Field-Effect-Transistor) 122, and the gate of the nMOSFET 124 is at VCCL. The differential pair of transistors 122 and 124 is coupled to the cross coupled pMOSFETs 126 and 128. The cross coupled transistors 126 and 128 have their source terminals connected to the VCCH power rail, and the output port 130 is taken at the drain of the transistor 122.
The transistors 128 and 126 are sized to be relatively weak compared to the other transistors. The ratios of transistor sizes are chosen to ensure proper operation. Operation of the cross-coupled voltage level shifter of FIG. 1A is well known and need not be described in detail. However, it is to be noted that as the input logic signal transitions from HIGH (VCCL) to LOW (VSS) or from LOW (VSS) to HIGH (VCCL), there is contention among the cross coupled pMOSFETs 126 and 128 and their respectively coupled nMOSFETs 122 and 124. This inherent contention issue arises irrespective of the shifting range VCCH-VCCL as long as VCCH is greater than VCCL, but the contention problem becomes more severe as the shifting range VCCH-VCCL becomes greater, and is particularly worsened if VCCL is near the transistor threshold voltage.
As a result, the output logic signal of a conventional voltage level shifter may be distorted, and the output logic signal may ultimately stop toggling all together as the maximum input logic signal voltage decreases further. FIG. 1B provides an example of the input and output logic signals for the circuit of FIG. 1A, where in FIG. 1B the input logic signal is denoted as “IN” and the output logic signal is denoted as “OUT”. (FIGS. 1A and 1B are disclosed in U.S. Pat. No. 6,677,798 B2, and are representative of conventional voltage level shifters with cross-coupled pMOSFETs.) Determining the appropriate ratio of the transistors to ensure reliable functioning and good timing behavior across all PVT (Process-Voltage-Temperature) corners can be a challenge.